This invention is related to digital counters in general and more particularly to an improved high speed Gray code generator.
In the electronic computing art, various codes are utilized in addition to binary code. One such code is what is known as the Gray code. When using the Gray code, there are instances where digital counting in this code must be accomplished. Historically, Gray code counters have suffered from two problems. They tend to have a limited frequency of operation and are logically complex and difficult to understand. The first of these problems is the requirement for existing Gray counters in the prior art to include a feedback network from the more significant stages to the less significant stages coupled with a feedforward network from the less significant stages to the more significant stages in order to properly advance the count.
The second problem is that of having logic gate configurations at each stage that are unique on a per stage basis and which become progressively larger as the number of stages increases. This leads to a difficulty in understanding the logic and a difficulty in troubleshooting.
There are two circuits recently introduced on the market which may not be considered prior art to the present invention. These are elements, one manufactured by Plessey Semiconductors, known as Gray Code Counter, Plessey Part No. SP520B which is a library element, modulus 5 counter, and one logic macrocell design manufactured by LSI Logic Corp. known as a Modulo 256 Gray Counter, Design #C86, at p. 18-47 of the 1984 CMOS Macrocell Manual which also can be considered a library element counter. However, they still suffer from the first problem and consequently share the disadvantage that, as the number of bits in the counter increases, its frequency of operation decreases.
Thus, even in multi-stage counters utilizing the Plessey or LSI Logic semiconductor devices, there are severe frequency limitations. With the other types of prior art Gray counter in which discrete components or gates and flip-flops of integrated circuits are used to construct the counter, a device is obtained in which each stage may be different from every other stage and in which the logic unique to each stage grows in size and complexity as the number of stages increases.
As a result, all of the old methods have comparatively low frequencies of operation with the necessary delay between successive counts that increases in roughly linear fashion as the number of counting stages increases. The degree of linearity of this increase and delay is dependent on the exact implementation of the feedback and feedforward control logic networks.
In addition, in multi-stage devices that do not employ the Plessey or LSI Logic integrated circuit, the increase in component count and logic complexity leads to larger and more complex designs which are more difficult to understand and service.
In view of these problems, it is the object of the present invention to provide a Gray code generator which does not require a feedback network from the more significant stages to the less significant stages and which does not require a feedforward network from the less significant stages to the more significant stages.
Furthermore, it is the object to provide a true, stage-by-stage, library element design, i.e., a design in which all stages, except for the most significant stage, are identical.
It is an additional object to provide a design in which the frequency of operation is unaffected by the number of stages.